Semiconductor devices and interconnections continue to shrink in feature size, leading to many unique problem. On one hand, topography is created as a result of device fabrication such as recessed oxide isolation, formation of gate electrode and sequential process of depositing and etching layers to form different regions, anneals and implants. In the current state of the art CMOS devices, the gate electrode can be 3-5 KA thick, has a nominal channel length of less than 2500 A and source/drain regions of comparable minimum widths. FIG. 1 is a simplified view of a prior art field effect transistor device.
A silicon substrate 100, has oxide isolation trenches 110 formed, the trenches 110 is etched and filled with the insulator. This provides a planar substrate to start forming the devices. The gate stack consists of a gate insulator 130 and a gate electrode 140 which is typically polysilicon with a cladding of a silicide for lowering the sheet resistivity. The gate electrode needs to be insulated from the electrode contacting the source/drain regions, which involves formation of sidewall insulators 135 (spacers) which increases the aspect ratio of the gap 180 between two closely spaced gate stacks. Responsive to this miniaturization and high aspect ratio of features and resulting gaps 170, 180 gap-fill insulating materials, vertical interconnects (studs S1) and planarization of insulator 150, 160 at each level are used. A first requirement of the insulator/process is its ability to fill narrow spaces and high aspect ratio grooves without voids.
In a contact stud process, vertical openings are etched to diffusion and gate electrode surfaces at different heights. In order to satisfactorily etch holes of different depths, while minimizing damage to underlying gate electrode or diffusions, the contact insulator typically consists of two layers, a bottom slow etching layer and a top faster etching layer. In a typical process, the bottom layer is conformally deposited and is kept to a small thickness and is usually a plasma deposited silicon dioxide or silicon nitride. Therefore a faster etching top layer compared to slower etching bottom PECVD silicon dioxide layer or silicon nitride layer is highly desirable.
Another desirable requirement for insulators adjacent to devices is that they be effective barrier to alkali ions and preferably to moisture. Two kinds of materials are effective for this. One kind form good diffusion barriers to alkali ions or water such as silicon nitride. The other material reacts with alkali ions and ties it up as a compound. An example of the latter is P doped silicon dioxide, which for example, reacts with free Na ion and forms sodium phosposilicate. SiN is used as a thinner layer because of its higher film stress and its high dielectric constant. However, P doped SiO.sub.2, usually as PSG or BPSG, is used in thicker layers. P doped oxides are increasingly preferred for contact insulation applications for their gettering effectiveness and their faster etch rates and polish rates compared to undoped silicon dioxide or silicon nitride. However, these properties of P doped oxides are influenced by deposition processes, amount of P and sometimes how phosphorus resides in the structure. Further, the amount of P that can be incorporated is limited because of the deposition process limitations or the concern that the resulting film can be hygrospic and be chemically attacked easily. Boron is sometimes added to SiO.sub.2 in addition to P to reduce the glass reflow temperature and to modify the film's mechanical stress.
Flowable gap-fill materials have been available and are known by the general name spin on glass (SOG). The SOG materials tend to crack on curing and can not be used except as thin layers. A new class of materials called FOx for flowable oxide, based on hydrogen silsesquioxane appears to have good fill properties, but is not effective as ionic barrier. U.S. Pat. No. 5,085,893 teaches heating the silsesquioxane layer in oxygen to form a resulting silicon dioxide layer which is ceramic like. U.S. Pat. No. 5,530,293 teaches the use of carbon free silsesquioxane for forming trench isolation fills, but recommend use of curing in a hydrogen ambient. The resulting films from both the above teachings are silicon dioxide films that do not provide a barrier against sodium or alkaline impurities, desired for insulation applications adjacent to the silicon device.
Chien et al. (U.S. Pat. No. 5,496,776) describes an ion implantation process, by which any of the following species, Si, Ar, P, B, O, N or F implanted into a spin on glass layer to reduce susceptibility for moisture absorption and outgassing from the spin-on-glass layer. By implanting P into the spin-on-glass, one would expect improvement in the alkali ion barrierproperties of the spin-on-glass or FOx, but implanting is expensive and can not be done selectively. U.S. Pat. No. 4,455,384 issued to the United States of America, Department of Energy, discloses that chemically durability of alkali phosphate glasses is improved by incorporation of up to 23 weight percent of nitrogen. The patent claimed that the addition of nitrogen to phosphate glasses create a more highly cross-linked (PO.sub.4).sub.n which reduced the TCE and increased the softening point. U.S. Pat. No. 4,455,384 is not directly relevant to the present invention as the glasses used in this patent have very low SiO.sub.2 content and is primarily made of P.sub.2 O.sub.5, but points to the benefit of adding nitrogen to high phosphate glass. All of these above materials and processes fail to meet one or more of the requirements discussed earlier.
Therefore, there is still a need for an insulator and process that can fill high aspect ratio grooves, form good barriers to alkali ions and finally allow for having differential etch and polish rates with other insulators.